Fin field effect transistors (FinFETs) have improved performance, or reduced supply voltage, and can significantly reduce the short channel effect. But, FinFETs also have some drawbacks that need to be overcome.
For N-channel metal oxide semiconductor (NMOS) and P-channel metal oxide semiconductor (PMOS), raised source and drain need to be formed. Among them, silicon germanium (SiGe) is used in PMOS devices, and silicon carbide (SiC) is used for NMOS devices. SiGe and SiC may introduce greater channel stress and reduce the contact resistance.
However, the epitaxial body formed as a source or a drain at the edge of the fin has an irregular form that affects the uniformity and performance of the device. Therefore, it is presently necessary to form a dummy gate to cover the edge of an active area of the fin, thereby avoiding irregular epitaxial problems.
FIG. 1A is a cross-sectional view of a semiconductor device according to the prior art. Referring to FIG. 1A, the semiconductor device includes fins 101, a shallow trench isolation (STI) 105 between fins 101, a dummy gate 102 on fins 101, a dummy gate 103 on STI 105, and a spacer material 104 on sidewalls of the dummy gates. In order to reduce the surface area of a design circuit, a single dummy gate 103 is formed on STI 105. But this causes the problem that spacer material 104 does not completely cover the edge of the fins, resulting in irregularities in the epitaxial body at the edge of the fins (as shown by the dotted circle in FIG. 1A), thereby affecting the device performance.
In order to solve the above-described problems, a non-recessed STI 105 process is required for the design of a single dummy gate, and may be referred to as a single diffusion break process, as shown in FIG. 1B.